One of the major difficulties in moving towards higher A/D conversion rates is the decreased available settling time for amplifiers. In older process generation designs, linear behavior dominates amplifier settling. Due to higher transition frequency (fT) transistors in deep sub-micron complementary metal oxide semiconductor (CMOS) layouts, slew behavior can dominate.
Amplifiers that employ “push-pull,” or “class AB,” topologies can efficiently achieve high-speed settling while driving large capacitive loads. FIGS. 1 and 2 are diagrams of prior art circuits employing, respectively, a common-source push-pull topology and a common-drain push-pull topology. An advantage of push-pull amplifiers like those shown is that a large transient current can be made available without consuming a large standing current. Such push-pull amplifiers can be made efficient by introducing a level-shift between the nominal input voltage and the desired gate voltages. In the circuits of FIGS. 1 and 2, voltage sources 102 and 104 are employed to introduce bias voltages VBIAS, P and VBIAS, N, respectively, between the input node 106 and the gates of the amplifier's complementary transistors. As illustrated in FIG. 3, this type of level-shifting can also be applied to other amplifier topologies, such as a level-shifted Class A amplifier.
Active level-shifting between the input voltage and gate voltages has been proposed in Gray, P. et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley, 2001, p. 364, which is incorporated herein by reference in its entirety. In CMOS technologies, switched-capacitor level shifting, such as that illustrated in FIG. 4, has also been used. Examples of such uses are described in Allen, P. and Holberg, D., CMOS Analog Circuit Design, New York: HRW, 1987, pp. 509-511; Hosticka, B., “Dynamic CMOS Amplifiers,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 887-894, October 1980; Palmisano, G. and Pennisi, S., “Dynamic Biasing for True Low-Voltage CMOS Class AB Current-Mode Circuits,” IEEE Trans. on Circuits and Systems, vol. 47, pp. 1569-1575, December 2000; Fayomi, C. J. B. et al, “A design strategy for a 1-V rail-to-rail input/output CMOS opamp,” 2001 Int. Symposium on Circuits and Systems, vol. 1, pp. 639-642, each of which is incorporated herein by reference in its entirety.
In the example of FIG. 4, charged capacitors 402, 404 are selectively connected between the input node 406 and the gates of complementary transistors 408, 410. Switched-capacitor level-shifting thus allows direct connections between the input and high impedance nodes (transistor gates in the illustrated example). Compared to active level-shifting, switched-capacitor level-shifting is power efficient and eliminates parasitic poles in the signal path.
In order to employ capacitive level-shifting, the proper charge needs to be applied to the level-shift capacitors 402, 404. One previously used technique for applying such charge is shown in FIG. 5. In this configuration, a charge-refreshing capacitor CREF is used to supply the needed charge on a level-shift capacitor CLS. In particular, during a first phase Φ1, switches 502, 504 are closed and switches 505, 507 are opened, thus allowing charge from the charge-refreshing capacitor CREF to be transferred to level-shift capacitor CLS. During a second phase Φ2, the switches 502, 504 are opened and the switches 505, 507 are closed, so that the voltage on the level-shift capacitor CLS is introduced between the input node 510 and the gate of NMOS transistor 512, and the charge-refreshing capacitor CREF is recharged when its plates are connected to a reference voltage node 506 and a bias voltage node 508.